EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 189

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 6–28. Counter Cascading
Note to
(1)
Altera Corporation
November 2007
n = 6 or n = 9
Figure
6–28:
VCO Output
VCO Output
VCO Output
VCO Output
VCO Output
VCO Output
Each PLL has one pre-scale counter, n, and one multiply counter, m, with
a range of 1 to 512 for both m and n. The n counter does not use duty-cycle
control because the only purpose of this counter is to calculate frequency
division. There are seven generic post-scale counters per Left/Right PLL
and ten post-scale counters per Top/Bottom PLL that can feed GCLKs,
RCLKs, or external clock outputs. These post-scale counters range from
1 to 512 with a 50% duty cycle setting. The high- and low-count values for
each counter range from 1 to 256. The sum of the high- and low-count
values chosen for a design selects the divide value for a given counter.
The Quartus II software automatically chooses the appropriate scaling
factors according to the input frequency, multiplication, and division
values entered into the altpll megafunction.
Post-Scale Counter Cascading
The Stratix III PLLs support post-scale counter cascading to create
counters larger than 512. This is automatically implemented in the
Quartus II software by feeding the output of one C counter into the input
of the next C counter as shown in
C0
C1
C2
C3
C4
Cn
Clock Networks and PLLs in Stratix III Devices
(1)
Figure
from preceding
post-scale counter
Stratix III Device Handbook, Volume 1
6–28.
6–39