EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 165

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
The multiplexer select lines are set in the configuration file (SRAM object
file [.SOF] or programmer object file [.POF]) only. Once programmed,
this block cannot be changed without loading a new configuration file
(.SOF or .POF). The Quartus II software automatically sets the
multiplexer select signals depending on the clock sources selected in the
design.
Figure 6–9. Clock Input Multiplexer Logic for L2, L3, T1, T2, B1, B2, R2, and
R3 PLLs
Notes to
(1)
(2)
(3)
GCLK / RCLK input (3)
The input clock multiplexing is controlled through a configuration file (.SOF or
.POF) only and cannot be dynamically controlled in user mode operation.
n=0 for L2 and L3 PLLs; n=4 for B1 and B2 PLLs; n=8 for R2 and R3 PLLs, and n=12
for T1 and T2 PLLs.
The global (GCLK) or regional (RCLK) clock input can be driven by an output from
another PLL, a pin-driven global or regional clock, or through a clock control block
provided the clock control block is fed by an output from another PLL or a pin
driven dedicated global or regional clock. An internally generated global signal or
general purpose I/O pin cannot drive the PLL.
Adjacent PLL output
Figure
clk[n+3..n] (2)
6–9:
Clock Networks and PLLs in Stratix III Devices
4
4
Stratix III Device Handbook, Volume 1
(1)
(1)
inclk0
inclk1
To the clock
switchover blo
6–15