EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 877

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS II
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
RCLK input adder
RCLK PLL input adder
Table 1–142. EP3SE260 Row Pins Output Timing Parameters (Part 4 of 4)
Table 1–143. EP3SE260 Column Pin Delay Adders for Regional Clock
Table 1–144. EP3SE260 Row Pin Delay Adders for Regional Clock (Part 1 of 2)
I/O Standard
Parameter
Parameter
Strength
Current
12mA
16mA
Industrial Commercial V
Industrial
—
—
—
—
Table 1–143
values that should be added to GCLK values. These adder values are
used to determine I/O timing when I/O pin is driven using regional
clock. This applies for all I/O standards supported by Stratix III devices.
Table 1–143
Regional Clock.
Table 1–144
Regional Clock in Stratix III devices.
—
—
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
Fast Model
Fast Model
Commercial
Parameter
-0.011
1.956
1.888
0.001
1.732
1.705
and
specifies EP3SE260 Column Pin delay adders when using the
specifies EP3SE260 Row Pin delay adders when using the
t
t
t
t
CO
CO
CO
CO
Stratix III Device Datasheet: DC and Switching Characteristics
Table 1–144
Industrial Commercial
CCL
V
CCL
—
—
—
—
-2
—
—
—
—
=1.1V V
-2
—
—
=1.1V
Fast Model
show EP3SE260 regional clock (RCLK) adder
CCL
3.293
3.158
0.138
0.134
V
3.100
1.442
3.098
1.438
-3
=1.1V V
CCL
2.928
2.776
Stratix III Device Handbook, Volume 2
-3
=1.1V
CCL
3.632
0.227
0.223
V
3.47
1.1V
-4
CCL
=1.1V V
V
—
—
—
—
-2
CCL
3.175
3.036
=
-4
=1.1V
V
5.553 5.896 5.721 6.060
2.677 2.748 2.711 2.697
5.545 5.888 5.713 6.052
2.669 2.740 2.703 2.689
1.1V
CCL
-3
CCL
=
0.184
3.46
3.31
0.18
=1.1V V
V
V
1.1V
CCL
CCL
-4
3.041
2.902
-4L
=1.1V
-4L
=
V
1.1V
CCL
CCL
3.421
3.272
0.399
0.393
1–365
=0.9V
=
-4L
V
0.9V
Units
CCL
ns
ns
=
Units
ns
ns
ns
ns
Units
ns
ns
ns
ns