EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 356

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Power-On Reset Circuitry
Figure 10–2. Transistor Level Diagram of a Stratix III Device I/O Buffers
Notes to
(1)
(2)
Power-On Reset
Circuitry
10–4
Stratix III Device Handbook, Volume 1
This is the logic array signal or the larger of either the V
This is the larger of either the V
Figure
10–2:
n+
Logic Array
The POR circuit monitors the voltage level of power supplies (V
V
device is in user mode. The weak pull-up resistor (R) in the Stratix III
input/output element (IOE) keeps the I/O pins from floating. The 3.3-V
tolerance control circuit permits the I/O pins to be driven by 3.3 V before
V
the I/O pins from driving out when the device is not in user mode.
Figure 10–2
I/O buffers. This design prevents leakage current from I/O pins to the
V
if the I/O pad voltage is higher than V
voltage spikes during hot insertion. The V
3.3-V tolerant circuit capacitance.
When power is applied to a Stratix III device, a power-on-reset event
occurs if the power supply reaches the recommended operating range
within a certain period of time (specified as a maximum power supply
ramp time; t
devices is 100 ms while the minimum power supply ramp time is 50 μs.
Stratix III devices provide a dedicated input pin (PORSEL) to select a POR
delay time of 12 ms or 100 ms during power-up. When the PORSEL pin is
connected to ground, the POR delay time is 100 ms. When the PORSEL
pin is set to high, the POR delay time is 12 ms.
p-well
Signal
CCPD
CCIO
CCIO
CCIO
, V
, V
supply when V
or V
CC
CCPGM
n+
, V
PAD
shows a transistor-level cross section of the Stratix III device
RAMP
CCPD
signal.
and V
V
). The maximum power supply ramp time for Stratix III
, and/or V
PAD
CCIO
CCPT
CCIO
) and keeps the I/O pins tri-stated until the
is powered before the other voltage supplies or
p+
or V
CCPGM
PAD
(1)
signal.
supplies are powered, and it prevents
n-well
CCIO
V
CCIO
p+
PAD
. This also applies for sudden
leakage current charges the
(2)
n+
p-substrate
Altera Corporation
October 2007
CC
, V
CCL
,