EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 333

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 9–15. Bit Orientation in Quartus II Software
Altera Corporation
November 2007
inclock/outclock
data in
Differential Data Orientation
There is a set relationship between an external clock and the incoming
data. For operation at 1 Gbps and SERDES factor of 10, the external clock
is multiplied by 10, and phase-alignment can be set in the PLL to coincide
with the sampling window of each data bit. The data is sampled on the
falling edge of the multiplied clock.
orientation of the ×10 mode.
Differential I/O Bit Position
Data synchronization is necessary for successful data transmission at
high frequencies.
operation. These figures are based on the following:
■
■
■
For other serialization factors, use the Quartus II software tools and find
the bit position within the word. The bit positions after deserialization are
listed in
SERDES factor equals clock multiplication factor
Edge alignment is selected for phase alignment
Implemented in hard SERDES
Table
High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
MSB
9
9–3.
Figure 9–16
8
7
6
shows the data bit orientation for a channel
10 LVDS Bits
5
Figure 9–15
4
Stratix III Device Handbook, Volume 1
3
2
shows the data bit
1
LSB
0
9–17