EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 94

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Design Considerations
Design
Considerations
4–20
Stratix III Device Handbook, Volume 1
Input/Output Clock Mode
Stratix III TriMatrix memory blocks can implement input/output clock
mode for true and simple dual-port memories. In this mode, an input
clock controls all registers related to the data input to the memory block
including data, address, byte enables, read enables, and write enables. An
output clock controls the data output registers. Asynchronous clears are
available on output latches and output registers only.
Read/Write Clock Mode
Stratix III TriMatrix memory blocks can implement read/write clock
mode for simple dual-port memories. In this mode, a write clock controls
the data-input, write-address, and write-enable registers. Similarly, a
read clock controls the data-output, read-address, and read-enable
registers. The memory blocks support independent clock enables for both
the read and write clocks. Asynchronous clears are available on data
output latches and registers only.
Single Clock Mode
Stratix III TriMatrix memory blocks can implement single-clock mode for
true dual-port, simple dual-port, and single-port memories. In this mode,
a single clock, together with a clock enable, is used to control all registers
of the memory block. Asynchronous clears are available on output latches
and output registers only.
This section describes guidelines for designing with TriMatrix memory
blocks.
Selecting TriMatrix Memory Blocks
The Quartus II software automatically partitions user-defined memory
into embedded memory blocks by taking into account both speed and
size constraints placed on your design. For example, the Quartus II
software may spread out a memory across multiple memory blocks when
resources are available in order to increase the performance of the design.
You can manually assign the memory to a specific block size via the RAM
MegaWizard.
MLABs can implement single-port SRAM through emulation via the
Quartus II software. Emulation results in minimal additional logic
resources being used. Because of the dual-purpose architecture of the
MLAB, it only has data input registers and output registers in the block.
MLABs gain input address registers and additional optional data output
registers from adjacent ALMs by using register packing.
Altera Corporation
November 2007