EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 156

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Clock Networks in Stratix III Devices
Figure 6–5. Stratix III Dual-Regional Clock Region
6–6
Stratix III Device Handbook, Volume 1
In order to form the entire device clock region, a source (not necessarily a
clock signal) drives a global clock network that can be routed through the
entire device. This clock region has the maximum delay compared to
other clock regions but allows the signal to reach every destination within
the device. This is a good option for routing global reset/clear signals or
routing clocks throughout the device.
In order to form a regional clock region, a source drives a single-quadrant
of the device. This clock region provides the lowest skew within a
quadrant and is a good option if all destinations are within a single device
quadrant.
To form a dual-regional clock region, a single source (a clock pin or PLL
output) generates a dual-regional clock by driving two regional clock
networks (one from each quadrant). This technique allows destinations
across two device quadrants to utilize the same low-skew clock. The
routing of this signal on an entire side has approximately the same delay
as in a regional clock region. Internal logic can also drive a dual-regional
clock network. Corner PLL outputs only span one quadrant and hence
cannot generate a dual-regional clock network.
dual-regional clock region.
Clock pins or PLL outputs
can drive half of the device to
create side-wide clocking
regions for improved
interface timing.
Figure 6–5
Altera Corporation
November 2007
shows the