EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 35

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Introduction
Logic Array
Blocks
Altera Corporation
October 2007
SIII51002-1.2
This chapter describes the features of the logic array block (LAB) in the
Stratix
blocks known as adaptive logic modules (ALMs) that can be configured
to implement logic functions, arithmetic functions, and register functions.
Each LAB consists of ten ALMs, carry chains, shared arithmetic chains,
LAB control signals, local interconnect, and register chain connection
lines. The local interconnect transfers signals between ALMs in the same
LAB. The direct link interconnect allows a LAB to drive into the local
interconnect of its left and right neighbors. Register chain connections
transfer the output of the ALM register to the adjacent ALM register in an
LAB. The Quartus
adjacent LABs, allowing the use of local, shared arithmetic chain, and
register chain connections for performance and area efficiency.
shows the Stratix III LAB structure and the LAB interconnects.
®
III core fabric. The logic array block is composed of basic building
®
II Compiler places associated logic in an LAB or
Adaptive Logic Modules in
2. Logic Array Blocks and
Stratix III Devices
Figure 2–1
2–1