EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 83

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EP3SE50F780I3N

Manufacturer Part Number
EP3SE50F780I3N
Description
Stratix III
Manufacturer
Altera
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Figure 4–6. ECC Block Diagram of the M144K
Memory Modes
Altera Corporation
November 2007
Data Input
64
64
SECDED
Encoder
64
1
1
Figure 4–6
Stratix III TriMatrix memory blocks allow you to implement fully
synchronous SRAM memory in multiple modes of operation. M9K and
M144K blocks do not support asynchronous memory (unregistered
inputs). MLABs support asynchronous (flow-through) read operations.
Depending on which TriMatrix memory block you target, the following
modes may be used:
Single-port
Simple dual-port
True dual-port
Shift-register
ROM
FIFO
8
You cannot use the byte enable feature when ECC is engaged.
Read during write “old data” mode is not supported when ECC
is engaged.
shows a block diagram of the ECC block of the M144K.
72
TriMatrix Embedded Memory Blocks in Stratix III Devices
RAM
Array
72
64
64
Stratix III Device Handbook, Volume 1
Data Output
Correction
Error
Block
8
SECDED
Encoder
64
Locator
Error
64
8
8
Comparator
8
Status Flags
Generator
Flag
3
4–9

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