HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 101

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Note:
Instruction
EXTS.B
EXTS.W Rm,Rn
EXTU.B
EXTU.W Rm,Rn
MAC.L
MAC.W
MUL.L
MULS.W Rm,Rn
MULU.W Rm,Rn
NEG
NEGC
SUB
SUBC
SUBV
*
Rm,Rn
Rm,Rn
@Rm+, @Rn+
@Rm+, @Rn+
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
The number of execution cycles indicated within the parentheses ( ) are required when
the operation result is read from the MACH/MACL register immediately after the
instruction.
Instruction Code Operation
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
0000nnnnmmmm1111
0100nnnnmmmm1111
0000nnnnmmmm0111
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
0011nnnnmmmm1000
0011nnnnmmmm1010
0011nnnnmmmm1011
A byte in Rm is sign-extended
→ Rn
A word in Rm is sign-
extended → Rn
A byte in Rm is zero-extended
→ Rn
A word in Rm is zero-
extended → Rn
Signed operation of (Rn) ×
(Rm) + MAC → MAC, Rn + 4
→ Rn, Rm + 4 → Rm
32 × 32 + 64 → 64 bits
Signed operation of (Rn) ×
(Rm) + MAC → MAC, Rn + 2
→ Rn, Rm + 2 → Rm
16 × 16 + 64 → 64 bits
Rn × Rm → MACL
32 × 32 → 32 bits
Signed operation of Rn × Rm
→ MACL
16 × 16 → 32 bits
Unsigned operation of
Rn × Rm → MACL
16 × 16 → 32 bits
0–Rm→Rn
0–Rm–T→Rn, Borrow→T
Rn–Rm→Rn
Rn–Rm–T→Rn, Borrow →T
Rn–Rm→Rn, Underflow→T
Rev. 1.00, 02/04, page 63 of 804
Privileged
Mode
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Cycles T Bit
1
1
1
1
2 (to 5)* 
2 (to 5)* 
2 (to 5)* 
1 (to 3)* 
1 (to 3)* 
1
1
1
1
1
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Borrow
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Borrow
Underflow