HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 596

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Notes: 1. FIFO full bits of EP2o and EP6 and FIFO empty bits of EP2i and EP5 are status bits
20.3.2
ISR selects the interrupt request pin to output the IFR0 interrupt. The USB function module has
two interrupt request signals (INT0N and INT1N) to output an interrupt request to the interrupt
controller (INTC). If the corresponding bit in ISR0 is cleared to 0, an INT0N interrupt request will
be issued and an interrupt request is issued from the INT1N pin when set to 1. INT0N and INT1N
interrupt request signals correspond to USBFI0 and USBFI1 of the interrupt controller (INTC),
respectively.
In the initial value, each of interrupt source of the interrupt flag register is issued from the INT0N
interrupt request signal.
Rev. 1.00, 02/04, page 558 of 804
Bit
1
0
2. The USB connection status (bit 28) is a bit indicating the state of the USB_VBUS pin,
Bit Name
EP0i TR
EP0i TS
Interrupt Select Register 0 (ISR0)
indicating the FIFO states, so they cannot be cleared.
so it cannot be cleared. Output of an interrupt is not carried out either.
Initial
Value
0
0
R/W
R/W
R/W
Description
EP0i Transfer Request
[Setting condition]
•
[Clearing conditions]
•
•
EP0i Transmit Complete
[Setting condition]
•
[Clearing conditions]
•
•
When IN token is issued from the host to EP0i and the
FIFO buffer is empty.
At a reset
When 0 is written to by CPU
When data to be transmitted to the host is written to
EP0i, then data is normally transferred from the
function to the host, and an ACK handshake is
returned.
At a reset
When 0 is written to by CPU