HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 305

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Burst Read: A burst read occurs in the following cases with this LSI.
• Access size in reading is larger than data bus width.
• 16-byte transfer in cache miss.
• 16-byte transfer in DMAC (access to non-cacheable region)
This LSI always accesses the SDRAM with burst length 1. For example, read access of burst
length 1 is performed consecutively 8 times to read 16-byte continuous data from the SDRAM that
is connected to a 16-bit data bus.
Table 9.10 shows the relationship between the access size and the number of bursts.
Table 9.10 Relationship between Access Size and Number of Bursts
Figures 9.12 and 9.13 show a timing chart in burst read. In burst read, an ACTV command is
output in the Tr cycle, the READA command is issued in the Tc1 to Tc7 cycles, the READA
command is issued in the Tc8 cycle, and the read data is received at the rising edge of the external
clock (CKIO) in the Td1 to Td8 cycles. The Tap cycle is used to wait for the completion of an
auto-precharge induced by the READ command in the SDRAM. In the Tap cycle, a new
command will not be issued to the same bank. However, access to another CS space or another
bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the TRP1
and TRP0 bits of the CS3WCR register.
In this LSI, wait cycles can be inserted by specifying each bit in the CS3WCR register to connect
the SDRAM in variable frequencies. Figure 9.13 shows an example in which wait cycles are
inserted. The number of cycles from the Tr cycle where the ACTV command is output to the Tc1
cycle where the READA command is output can be specified using the TRCD1 and TRCD0 bits
of the CS3WCR register. If the TRCD1 and TRCD0 bits specify two cycles or more, a Trw cycle
where the NOT command is issued is inserted between the Tr cycle and Tc1 cycle. The number of
cycles from the Tc1 cycle where the READA command is output to the Td1 cycle where the read
data is latched can be specified using the A3CL1 and A3CL0 bits of the CS3WCR register. The
number of cycles from Tc1 to Td1 corresponds to the synchronous DRAM CAS latency. The
CAS latency for the synchronous DRAM is normally defined as up to three cycles. However, the
CAS latency in this LSI can be specified as 1 to 4 cycles. This CAS latency can be achieved by
connecting a latch circuit between this LSI and the synchronous DRAM.
Data Bus Width
16 bits
Access Size
8 bits
16 bits
32 bits
16 bits
Rev. 1.00, 02/04, page 267 of 804
1
1
2
8
Number of Bursts