HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 373

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

The clock pulse generator blocks function as follows:
PLL Circuit 1: PLL circuit 1 multiplies the input clock frequency by 1, 2, 3 or 4 from the CKIO
pin. The multiplication rate is set using the frequency control register (FRQCR). When this is
done, the phases of the leading edge of the internal clock, bus clock, and peripheral clock are
controlled so that those will agree with the phase of the leading edge of the CKIO pin.
PLL Circuit 2: PLL circuit 2 doubles the input clock frequency from the crystal oscillator or
EXTAL pin. The multiplication rate is fixed according to the clock operating mode. The clock
operating mode is specified by the MD1 and MD2 pins. For details on clock operating mode, see
table 11.2.
Crystal Oscillator: The crystal oscillator is an oscillator circuit in which a crystal resonator is
connected to the XTAL pin or EXTAL pin. This can be used according to the clock operating
mode 6.
Divider 1: Divider 1 generates a clock at the operating frequency used by the internal, bus, or
peripheral clock. The operating frequency can be 1, 1/2, 1/3, 1/4, 1/6, 1/8, or 1/12 times the output
frequency of PLL circuit 1, as long as it stays at or above the clock frequency of the CKIO pin.
The division ratio is set in the frequency control register (FRQCR). *
Note: * Internal and peripheral clocks can be selected independently using the frequency
Clock Frequency Control Circuit: The clock frequency control circuit controls the clock
frequency using the MD1 and MD2 pins and the frequency control register (FRQCR).
Standby Control Circuit: The standby control circuit controls the states of the clock pulse
generator and other modules during clock switching or sleep, or standby modes.
Frequency Control Register: The frequency control register (FRQCR) has control bits assigned
for the following functions: clock output/non-output from the CKIO pin, the frequency
multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the
peripheral clock.
Standby Control Register: The standby control registers (STBCR, STBCR2 to STBCR4) have
bits for controlling the power-down modes. See section 13, Power-Down Modes, for more
information.
Memory Clock Control Register: The memory clock control register (MCCR) has the memory
clock in sleep and the control bits of 32-k clock oscillator for BT. For more information on
MCCR, see section 13, Power-Down Mode.
control register (FRQCR). However, even though it is the selectable combination, if the
number of operation frequencies which surpasses upper limit value of each operating
frequency is set, operation of this LSI can not be guaranteed. Since operation frequency
of bus clock should be the same as that of the CKIO, the division ratio is automatically
set using the multiplication rate of PLL circuit 1.
Rev. 1.00, 02/04, page 335 of 804