HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 339

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Common:
• DMA operation register (DMAOR)
• DMA extension resource selector 0 (DMARS0)
• DMA extension resource selector 1 (DMARS1)
10.3.1
SAR is a 32-bit readable/writable register that specifies the source address of a DMA transfer.
During a DMA transfer, this register indicates the next source address. When the data of an
external device with DACK is transferred in the single address mode, the SAR is ignored.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the
source address value. The SAR is undefined at reset and retains the current value in standby or
module standby mode.
10.3.2
DAR is a 32-bit readable/writable register that specifies the destination address of a DMA transfer.
This register includes count functions, and during a DMA transfer, this register indicates the next
destination address. When the data of an external device with DACK is transferred in the single
address mode, the DAR is ignored.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the
source address value. The DAR is undefined at reset and retains the current value in standby or
module standby mode.
10.3.3
DMATCR is a 32-bit readable/writable register that specifies the DMA transfer count (bytes,
words, or longwords). The number of transfers is 1 when the setting is H'00000001, 16777215
when H'00FFFFFF is set, and 16777216 (the maximum) when H'00000000 is set. During a DMA
transfer, this register indicates the remaining transfer count.
The upper eight bits of DMATCR will return 0 if read, and should only be written with 0. To
transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. The DMATCR is undefined at
reset and retains the current value in standby or module standby mode.
DMA Destination Address Register (DAR)
DMA Transfer Count Register (DMATCR)
DMA Source Address Register (SAR)
Rev. 1.00, 02/04, page 301 of 804