HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 556

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Note:
19.3.4
HISR indicates the status in various events that cause hardware interrupts. When an event occurs,
the host controller sets the corresponding bit in this register. When the bit is set to 1, a hardware
interrupt is generated while an interrupt is enabled and the MIE bit is set in the HcInterruptEnable
register (see section 19.3.5, HcInterruptEnable Register (HIER)). When an interrupt occurs, the
exception code (H'A00) of the host controller interrupt (USBHI) is set in the interrupt event
register 2 (INTEVT2) and the exception handling is started. For details on the interrupt event
register 2 (INTEVT2), see section 4, Exception Handling, and for details on the exception code
and interrupt processing of the host controller interrupt (USBHI), see section 8, Interrupt
Controller (INTC).
The host controller driver clears a specified bit in this register by writing 1 in the bit position to be
cleared. The host controller driver cannot set any of these bits. The host controller never clears
bits.
Rev. 1.00, 02/04, page 518 of 804
Bit
0
*
Bit Name
HCR
HcInterruptStatus Register (HISR)
TD is Transfer Descriptor.
Initial
Value
0
R/W
R/W
Description
Host Controller Request
This bit is set by the host controller driver to initiate the
software reset of the host controller. The system is
moved to the USB Suspend state in which most of the
operational registers are reset except for the next state
regardless of the functional state of the host controller.
For example, an access without the IR field in the
HcControl register and host bus are allowed. This bit is
cleared by the host controller upon completion of the
reset operation. The reset operation must be completed
within 10 µs. When this bit is set, it does not cause any
reset to the route hub and the next reset signal is not
output to the downstream port.
0: Cleared by the host controller at the completion of the
1: USB Suspend state
reset operation