HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 205

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

User break point trap:
• Conditions
• Types
• Save address
• Exception code
• Remarks
DMA address error:
• Conditions
• Types
• Save address
• Exception code
• Remarks
Note: Address error does not occurred in the USB host since the hardware automatically
When a break condition set in the user break controller is satisfied
Break (L bus) before instruction execution: Instruction synchronous, re-execution type
Operand break (L bus): Instruction synchronous, processing-completion type
Data break (L bus): Instruction asynchronous, processing-completion type
I bus break: Instruction asynchronous, processing-completion type
Re-execution type: An address of the instruction where a break occurs (a delayed branch
instruction address if an instruction is assigned to a delay slot)
Completion type: An address of the instruction following the instruction where a break occurs
(a delayed branch instruction destination address if an instruction is assigned to a delay slot)
H'1E0
For details on user break controller, refer to section 25, User Break Controller (UBC).
 Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
 Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n +
Instruction asynchronous, processing-completion type
An address of the instruction following the instruction where a break occurs (a delayed branch
instruction destination address if an instruction is assigned to a delay slot)
H'5C0
An exception occurs when a DMA transfer is executed while an illegal instruction address
described above is specified in the DMAC. Since the DMAC transfer is performed
asynchronously with the CPU instruction operation, an exception is also requested
asynchronously with the instruction execution. For details on DMAC, refer to section 10,
Direct Memory Access Controller (DMAC).
3)
recognizes the address and performs accessing data of enough bit length.
Rev. 1.00, 02/04, page 167 of 804