HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 381

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

11.5
The frequency of the internal clock and peripheral clock can be changed either by changing the
multiplication rate of PLL circuit 1 or by changing the division rates of divider 1. All of these are
controlled by software through the frequency control register. The methods are described below.
11.5.1
A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The on-
chip WDT counts the settling time.
1. In the initial state, the multiplication rate of PLL circuit 1 is 1.
2. Set a value that will become the specified oscillation settling time in the WDT and stop the
3. Set the desired value in the STC[2:0] bits. The division ratio can also be set in the IFC[2:0] and
4. The processor pauses internally and the WDT starts incrementing. The internal, bus, and
5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins
Note: When changing the clock frequency multiplication ratio, clear both UMCLKC bit and
11.5.2
The WDT will not count unless the multiplication rate is changed simultaneously.
1. In the initial state, IFC[2:0] = B'000 and PFC[2:0] = B'011
2. Set the IFC[2:0] and PFC[2:0] bits to the new division ratio. The values that can be set are
3. The clock is immediately supplied at the new division ratio.
WDT. The following must be set:
WTCSR register TME bit = 0: WDT stops
WTCSR register CKS2 to CKS0 bits: Division ratio of WDT count clock
WTCNT counter: Initial counter value
PFC[2:0] bits.
peripheral clocks stop and the WDT is supplied with the clock. The clock will continue to be
output at the CKIO pin.
operating again. The WDT stops after it overflows.
limited by the clock mode and the multiplication rate of PLL circuit 1. Note that if the wrong
value is set, the processor will malfunction.
XYMCLKC bit of memory clock control register (MCCR) to 0.
Changing the Frequency
Changing the Multiplication Rate
Changing the Division Ratio
Rev. 1.00, 02/04, page 343 of 804