HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 344

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 1.00, 02/04, page 306 of 804
Bit
5
4
3
2
1
Bit Name
TB
TS1
TS0
IE
TE
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W* Transfer End Flag
Descriptions
Transfer Bus Mode
This bit specifies the bus mode when DMA transfers data.
0: Cycle steal mode (Initial Value)
1: Burst mode
Transfer Size
TS1 and TS0 specify the size of data to be transferred.
Select the size of data to be transferred when the source
or destination is an on-chip peripheral module register of
which transfer size is specified.
00: Byte size
01: Word size (two bytes)
10: Longword size (four bytes)
11: 16-byte unit (four longword transfers)
Interrupt Enable
This bit specifies whether or not an interrupt request is
generated to the CPU at the end of the DMA transfer.
Setting this bit to 1 generates an interrupt request (DEI) to
the CPU when TE bit is set to 1.
0: Interrupt request is not generated
1: Interrupt request is generated
This bit shows that DMA transfer ends. TE is set to 1 when
data transfer ends when DMATCR becomes to 0.
TE bit is not set to 1 in the following cases.
•
•
This bit can only be cleared by writing 0 after reading 1.
Even if the DE bit is set to 1 while this bit is set to 1,
transfer is not enabled.
0: During the DMA transfer or DMA transfer has been
1: Data transfer ends by the specified count (DMACTR =
suspended
0)
Clearing condition: Writing 0 after TE = 1 read
DMA transfer ends due to an NMI interrupt or DMA
address error before DMATCR becomes to 0.
DMA transfer is ended by clearing the DE bit and DME
bit in DMA operation register (DMAOR).