HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 333

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

9.5.10
Usage Notes
Reset: The bus state controller (BSC) can be initialized completely only at power-on reset. At
power-on reset, all signals are negated and output buffers are turned off regardless of the bus cycle
state. All control registers are initialized.
In standby, sleep, and manual reset, control registers of the bus state controller are not initialized.
At manual reset, the current bus cycle being executed is completed and then the access wait state
is entered. If a 16-byte transfer is performed by a cache or if another LSI on-chip bus master
module is executed when a manual reset occurs, the current access is cancelled in longword units
because the access request is cancelled by the bus master at manual reset. If a manual reset is
requested during cache fill operations, the contents of the cache cannot be guaranteed. Since the
RTCNT continues counting up during manual reset signal assertion, a refresh request occurs to
initiate the refresh cycle. In addition, a bus arbitration request by the BREQ signal can be
accepted during manual reset signal assertion.
Some flash memories may specify a minimum time from reset release to the first access. To
ensure this minimum time, the bus state controller supports a 7-bit counter (RWTCNT). At
power-on reset, the RWTCNT is cleared to 0. After power-on reset, RWTCNT is counted up
synchronously together with CKIO and an external access will not be generated until RWTCNT is
counted up to H′007F. At manual reset, RWTCNT is not cleared.
Access from the Site of the LSI Internal Bus Master: There are three types of LSI internal
buses: a cache bus (L bus), internal bus (I bus), and peripheral bus. The CPU and cache memory
are connected to the cache bus. Internal bus masters other than the CPU and bus state controller
are connected to the internal bus. Low-speed peripheral modules are connected to the peripheral
bus. Internal memories other than the cache memory and debugging modules such as a UBC and
AUD are connected bidirectionally to the cache bus and internal bus. Access from the cache bus
to the internal bus is enabled but access from the internal bus to the cache bus is disabled. This
gives rise to the following problems.
On-chip bus masters such as DMAC other than the CPU can access internal memory other than
the cache memory but cannot access the cache memory. If an on-chip bus master other than the
CPU writes data to an external memory other than the cache, the contents of the external memory
may differ from that of the cache memory. To prevent this problem, if the external memory
whose contents is cached is written by an on-chip bus master other than the CPU, the
corresponding cache memory should be purged by software.
If the CPU initiates read access for the cache, the cache is searched. If the cache stores data, the
CPU latches the data and completes the read access. If the cache does not store data, the CPU
performs four contiguous longword read cycles to perform cache fill operations via the internal
bus. If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary
(4n + 2), the CPU performs four contiguous longword accesses to perform a cache fill operation
on the external interface. For a cache-through area, the CPU performs access according to the
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