HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 231

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

6.2.3
The X/Y memory is always accessed by I bus master modules such as the DMAC and USBH via
the I bus, which is a physical address bus. The 8/16/32-bit access is performed by the DMAC and
8/32-bit access is performed by the USBH. When accessing other than the P4 area (A31 to A29 =
B'111), three most significant bits of the address are internally set to B'000 even if the logic
addresses are specified other than P4 area. Therefore, access is performed through I bus.
6.3
6.3.1
In the event of simultaneous accesses to the same page from different buses, the conflict on the
pages occurs. Although each access is completed correctly, this kind of conflict tends to lower
X/Y memory accessibility. Therefore it is advisable to provide software measures to prevent such
conflict as far as possible. For example, conflict will not arise if different memory or different
pages are accessed by each bus.
6.3.2
The I bus is shared by several bus master modules. When the X/Y memory is accessed via the I
bus, a conflict between the other I-bus master modules may occur on the I bus. This kind of
conflict tends to lower X/Y memory accessibility. Therefore it is advisable to provide software
measures to prevent such conflict as far as possible. For example, by accessing the X/Y memory
by the CPU not via the I bus but from space P2 or Uxy via the L bus, conflict on the I bus can be
prevented.
6.3.3
When the X/Y memory is accessed via the I bus using the cache from the CPU and DSP, correct
operation cannot be guaranteed. If the X/Y memory is accessed while the cache is enabled
(CCR1.CE = 1), it is advisable to access the X/Y memory via the L bus from space P2 or Uxy. In
a program that requires high performance, it is advisable to access the X/Y memory from space P2
or Uxy.
The relationship described above is summarized in table 6.2.
Access from I Bus Master Module
Usage Notes
Page Conflict
Bus Conflict
Cache Settings
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