HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 341

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
22
21 to 18
17
16
Bit Name
TL

AM
AL
Initial
Value
0
All 0
0
0
R/W
R/W
R
R/W
R/W
Acknowledge Mode
Descriptions
Transfer End Level
This bit specifies the TEND signal output is high active or
low active. This bit is valid only in CHCR_0. This bit is
reserved in CHCR_1 to CHCR_3. The write value should
always be 0. If 1 is written to this bit, correct operation
cannot be guaranteed.
0: Low-active output of TEND
1: High-active output of TEND
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to this bit, correct operation
cannot be guaranteed.
AM specifies whether DACK is output in data read cycle or
in data write cycle in dual address mode.
In single address mode, DACK is always output regardless
of the specification by this bit.
This bit is valid only in CHCR_0. This bit is reserved in
CHCR_1 to CHCR_3. The write value should always be 0.
If 1 is written to this bit, correct operation cannot be
guaranteed.
0: DACK output in read cycle (Dual address mode)
1: DACK output in write cycle (Dual address mode)
Acknowledge Level
AL specifies the DACK (acknowledge) signal output is high
active or low active.
This bit is valid only in CHCR_0. This bit is reserved in
CHCR_1 to CHCR_3. The write value should always be 0.
If 1 is written to this bit, correct operation cannot be
guaranteed.
0: Low-active output of DACK
1: High-active output of DACK
Rev. 1.00, 02/04, page 303 of 804