HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 610

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

20.3.20 Data Status Register (DASTS)
DASTS indicates whether the transmit FIFO data register contains valid data. DASTS is set to 1
when data written to the transmit FIFO is enabled by writing PKTE in TRG to 1, and cleared to 0
when all data has been transmitted to the host. In case of a dual-configuration FIFO for endpoints
2i and 5, this bit is cleared to 0 when both sides are empty.
20.3.21 FIFO Clear Register (FCLR)
FCLR is a one shot register to clear the FIFO buffers for each endpoint. Writing 1 to a bit clears
the data in the corresponding FIFO buffer. Each bit in this register is automatically cleared to 0
after it is set to 1.
In case of the transmit FIFO, by writing data in the FIFO buffer, the data by which PKTE in TRG
is not written to 1 and the data enabled by writing 1 can be cleared. In case of the receive FIFO,
the unfixed data during reception and the data of which reception has not been completed can be
cleared.
Both sides of the dual-configuration FIFO buffers for EP2i, EP2o, EP3i, EP3o EP5, and EP6 can
be cleared.
The corresponding interrupt flag is not cleared by this clear instruction. Do not clear a FIFO buffer
during transmission.
Rev. 1.00, 02/04, page 572 of 804
Bit
7
6
5
4
3
2
1
0
Bit Name

EP5DE
EP4DE

EP2iDE
EP1DE

EP0iDE
0
0
0
0
0
Initial Value
0
0
0
R
R
R
R
R
R/W
R
R
R
Description
Reserved
This bit is always read as 0.
EP5 Data Enable
EP4 Data Enable
Reserved
This bit is always read as 0.
EP2i Data Enable
EP1 Data Enable
Reserved
This bit is always read as 0.
EP0i Data Enable