HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 607

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

20.3.11 EP3o Data Register (EPDR3o)
EPDR3o is a 120-byte 8-bit receive FIFO buffer for endpoint 3o. EPDR3o has a dual-buffer
configuration, and has a capacity of twice the maximum packet size. The number of receive byte is
displayed in the EPSZ3o register. The receive data is fixed when an SOF packet is received.
Accordingly, all receive data must be read until the next SOF packet is received. When the next
SOF packet is received, the FIFO side is automatically switched over, and the previous data will
not be possible to be read. This FIFO buffer can be initialized by means of EP3o CLR in FCLR.
Note: When an SOF packet cannot be received, an SOF interrupt is generated by an SOF marker
20.3.12 EP4 Data Register (EPDR4)
EPDR4 is a 16-byte 8-bit transmit FIFO buffer for endpoint 4. EPDR4 holds one packet of
transmit data for the interrupt transfer of endpoint 4. Transmit data is fixed by writing one packet
of data and setting EP4PKTE in TRG. When an ACK handshake is returned from the host after the
data has been transmitted, EP4TS in IFR0 is set. This FIFO buffer can be initialized by means of
EP4CLR in FCLR.
20.3.13 EP5 Data Register (EPDR5)
EPDR5 is a 64-byte 8-bit transmit FIFO buffer for endpoint 5. EPDR5 has a dual-buffer
configuration, and has a capacity of twice the maximum packet size. When transmit data is written
to this FIFO buffer and setting EP5PKTE in the trigger register, one packet of transmit data is
fixed, and the dual-FIFO buffer is switched over. Data can be transferred to this FIFO buffer by
DMA. This FIFO buffer can be initialized by means of EP5CLR in the FCLR register.
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
function. However, data in a frame which could not receive an SOF is invalid.
Bit Name
D7 to D0
Bit Name
D7 to D0
Bit Name
D7 to D0
Initial Value
Undefined
Initial Value
Undefined
Initial Value
Undefined
R/W
R
R/W
W
R/W
W
Description
Data register for endpoint 3o transfer
Description
Data register for endpoint 4 transfer
Description
Data register for endpoint 5 transfer
Rev. 1.00, 02/04, page 569 of 804