HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 533

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

In the initial programming of the external flash memory, the reset vector always selects a branch
to the address H'A0000000 (a virtual address as seen from the CPU) after the power-on reset
signal has been cancelled and area 0 in the external address space is accessed. The programming
program must thus be executed from a start address in area 0. In boot mode, however, addresses
H'00000000 to H'01FFFFFF are exclusively used for the boot function, so programming is
executed from the start address H'02000000. The maximum mounted area for this LSI is 16
Mbytes. Since the address range from H'02000000 to H'02FFFFFF is the shadow space for the
range from H'00000000 to H'00FFFFFF, if programming starts at address H'02000000, access can
be performed from address H'00000000 after boot mode has been cancelled.
Note: The state of the input on the BOOT_E pin input must not be changed except during a
17.4.2
The initial programming program of the external flash memory must be placed in the external host
before the boot function is used. The initial programming program must be prepared in accordance
with the programming algorithm for the external flash memory that is to be used.
The boot program starts preparing for the transfer of data to and from the external host over
channel 0 of the SCIF. After the necessary initial settings for the SCIF0 have been made, the bit
rate for use in transmission/reception is automatically adjusted to suit the external host. Figure
17.3 shows the procedure according to which boot processing is executed.
Automatic Adjustment Operation for SCIF0 Bit Transfer Rate: This LSI automatically adjusts
the bit transfer rate for transmission/reception to a value in the range between 9.6 kbps and 38.4
kbps. When this LSI is activated in boot mode, it measures the period of the low levels in the
synchronous data (H'00) which is continuously transmitted from the external host. Channel 0 in
the timer unit (TMU) is used for this low-period measurement. Here, the external host must set the
format for transfer between this LSI and the SCIF0 as 8-bit data, one stop bit, and no parity bit.
After the boot program has calculated the bit rate at which bits are being transferred from the
external host by using the measurement of the low period and the optimum setting has been made,
a single byte with the value H'00 is transmitted to the external host as notification of the end of the
bit-rate adjustment. After the external host has successfully received this notification of the end of
bit-rate adjustment, a single byte with the value H'55 must be returned to this LSI. After this LSI
has received this byte, it transmits a single byte with the value H'AA.
Note: If reception is not successful, execution enters an endless loop and the program will not
reset. If this state is changed, correct operation is not guaranteed.
react. In such a case, reinitiate boot mode after a reset, and repeat the above operations.
Procedure for Execution of Boot Processing
Rev. 1.00, 02/04, page 495 of 804