HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 158

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HD6417660

Manufacturer Part Number
HD6417660
Description
Renesas 32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. However, in case of a conditional
operation, they are not updated even though the specified condition is true and the operation is
executed. In case of an unconditional operation, they are always updated in accordance with the
operation result. The definition of a DC bit is selected by CS[2:0] (condition selection) bits in
DSR. The DC bit result is as follows:
Carry or Borrow Mode: CS[2:0] = B'000: The DC bit indicates that carry or borrow is
generated from the most significant bit of the operation result, except the guard-bit parts. Some
examples are shown in figure 3.11. This mode is the default condition. When the input data is
negative in a PABS or PNEG instruction, carry is generated.
Rev. 1.00, 02/04, page 120 of 804
Operation Sequence Example
PADD X0, Y0, A0
Stage
MA/DSP
EX
ID
IF
Slot
MOVX.W @R4+, X0
MOVX.W @R4+, X0
MOVX
Figure 3.10 Operation Sequence Example
1
MOVX & PADD
MOVX
2
Previous cycle result is used.
MOVX & PADD
Addressing
3
Addressing
MOVX
4
MOVX & PADD
5
6

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