HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 329

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

9.5.8
As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often
collides with the next data access when the read operation from devices with slow access speed is
completed. As a result of these collisions, the reliability of the device is low and malfunctions may
occur. A function that avoids data collisions by inserting wait cycles between continuous access
cycles has been newly added.
The number of wait cycles between access cycles can be set by bits IWW[1:0], IWRWD[1:0],
IWRWS[1:0], IWRRD[1:0], and IWRRS[1:0] in the CSnBCR register , and bits DMAIW[1:0] and
DMAIWA in CMNCR. The conditions for setting the wait cycles between access cycles (idle
cycles) are shown below.
1. Continuous accesses are write-read or write-write
2. Continuous accesses are read-write for different spaces
3. Continuous accesses are read-write for the same space
4. Continuous accesses are read-read for different spaces
5. Continuous accesses are read-read for the same space
6. Data output from an external device caused by DMA single transfer is followed by data output
7. Data output from an external device caused by DMA single transfer is followed by any type of
9.5.9
In bus arbitration, the LSI operates in two ways;
1. The LSI has the bus mastership in the normal state, and releases the bus mastership after
2. The LSI does not have the bus mastership in the normal state; it requests the bus mastership
In the case of the LSI with bus mastership in the normal state, this is called master mode. This LSI
supports master mode.
To prevent device malfunction while the bus mastership is transferred between master and slave,
the LSI negates all of the bus control signals before bus release. When the bus mastership is
received, all of the bus control signals are first negated and then driven appropriately. In this case,
output buffer contention can be prevented because the master and slave drive the same signals
with the same values. In addition, to prevent noise while the bus control signal is in the high
impedance state, pull-up resistors must be connected to these control signals.
Bus mastership is transferred at the boundary of bus cycles. Namely, bus mastership is released
immediately after receiving a bus request when a bus cycle is not being performed. The release of
from another device that includes this LSI (DMAIWA = 0)
access (DMAIWA = 1)
receiving a bus request from another device.
each time that external access is necessary.
Wait between Access Cycles
Bus Arbitration
Rev. 1.00, 02/04, page 291 of 804