HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 308

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Burst Write: A burst write occurs in the following cases in this LSI.
• Access size in writing is larger than data bus width.
• Copyback of the cache
• 16-byte transfer in DMAC (access to non-cacheable region)
This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1
is performed continuously 8 times to write 16-byte continuous data to the SDRAM that is
connected to a 16-bit data bus.
The relationship between the access size and the number of bursts is shown in table 9.10.
Figure 9.15 shows a timing chart for burst writes. In burst write, an ACTV command is output in
the Tr cycle, the WRIT command is issued in the Tc1 to Tc7 cycles, and the WRITA command is
issued to execute an auto-precharge in the Tc8 cycle. In the write cycle, the write data is output
simultaneously with the write command. After the write command with the auto-precharge is
output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the Tap cycle that
waits for completion of the auto-precharge induced by the WRITA command in the SDRAM. In
the Tap cycle, a new command will not be issued to the same bank. However, access to another
CSn space or another bank in the same SDRAM space is enabled. The number of Trw1 cycles is
specified by the TRWL1 and TRWL0 bits of the CS3WCR register. The number of Tap cycles is
specified by the TRP1 and TRP0 bits of the CS3WCR register.
Rev. 1.00, 02/04, page 270 of 804
D15 to D0
A23 to A0
Figure 9.15 Basic Timing for Synchronous DRAM Burst Write (Auto Pre-charge)
Note: * Address pin to be connected to the A10 pin of SDRAM.
RD/WR
DQMn
CKIO
A11*
RAS
CAS
CS3
Tr
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Trwl
Tap