HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 712

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

4. Access by a PREF instruction is handled as read access in longword units without access data.
5. If the L bus is selected, a break occurs on ending execution of the instruction that matches the
25.3.4
1. The break condition on an X/Y-memory bus cycle is specified only in channel B. If the XYE
2. When an X-memory address is selected as the break condition, specify an X-memory address
3. The timing of a data access break for the X memory or Y memory bus to occur is the same as a
25.3.5
1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break
2. In sequential break specification, the L/I/X/Y bus can be selected and the execution times
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Therefore, if including the value of the data bus when a PREF instruction is specified as a
break condition, a break will not occur.
break condition, and immediately before the next instruction is executed. However, when data
is also specified as the break condition, the break may occur on ending execution of the
instruction following the instruction that matches the break condition. If the I bus is selected,
the instruction at which the break will occur cannot be determined. When this kind of break
occurs at a delayed branch instruction or its delay slot, the break may not actually take place
until the first instruction at the branch destination.
bit in BBRB is set to 1, the break address and break data on X/Y-memory bus are selected. At
this time, select the X-memory bus or Y-memory bus by specifying the XYS bit in BBRB. The
break condition cannot include both X-memory and Y-memory at the same time. The break
condition is applied to an X/Y-memory bus cycle by specifying L bus/data access cycle/read or
write/word or no specified operand size (in bits 7 to 0) in the break bus cycle register B
(BBRB).
in the upper 16 bits in BARB and BAMRB. When a Y-memory address is selected, specify a
Y-memory address in the lower 16 bits. Specification of X/Y-memory data is the same for
BDRB and BDMRB.
data access break of the L bus. For details, see 5 in section 25.3.3, Break on Data Access
Cycle.
condition matches after a channel A break condition matches. A user break is not generated
even if a channel B break condition matches before a channel A break condition matches.
When channels A and B conditions match at the same time, the sequential break is not issued.
To clear the channel A condition match when a channel A condition match has occurred but a
channel B condition match has not yet occurred in a sequential break specification, clear the
SEQ bit in BRCR to 0.
break condition can be also specified. For example, when the execution times break condition
is specified, the break condition is satisfied when a channel B condition matches with BETR =
H'0001 after a channel A condition has matched.
Sequential Break
Break on X/Y-Memory Bus Cycle