HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 551

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

19.3.2
HCTLR specifies the operation mode for the host controller.
Bit
31 to 9
8
7
6
HcControl Register (HCTLR)
Bit Name
—
IR
HCFS1
HCFS0
Initial
Value
All 0
0
0
0
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0. The operation is not guaranteed if 1 is
written to these bits.
Interrupt Routine
Determines the issue of interrupts generated by the event
registered in the HcInterruptStatus register. The host
controller driver clears this bit at the same time as the
hardware reset, however, does not clear at the same time
as the software reset. The host controller driver uses this
bit as a tag to indicate the ownership of the host
controller.
0: All interrupts are issued to the interrupt mechanism of
1: Interrupts are issued to SMI.
Host Controller Function Status
The host controller driver detects whether the host
controller has started to transmit SOF after having read
the SF bit in the HcInterruptStatus register. This bit can
be changed only in the USB Suspend state by the host
controller. The host controller can move from the USB
Suspend state to the USB Resume state after having
detected the resume signal from the downstream port. In
the host controller, USB Suspend is entered after the
software reset so that USB Reset is entered after the
hardware reset. The former resets the route hub.
00: USB Reset
01: USB Resume
10: USB Operational
11: USB Suspend
the normal host bus.
Rev. 1.00, 02/04, page 513 of 804