HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 197

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

1. The contents of the SSR are restored into the SR to return to the processing state in effect
2. A delay slot instruction of the RTE instruction is executed.*
3. Control is passed to the address stored in the SPC.
The above operations from 1 to 3 are executed in sequence. During these operations, no other
exceptions may be accepted. By changing the SPC and SSR before executing the RTE instruction,
a status different from that in effect before the exception handling can also be specified.
Note: * For details on the CPU processing mode in which RTE delay slot instructions are
4.2.2
A vector address for general exceptions is determined by adding a vector offset to a vector base
address. The vector offset for general exceptions is H'00000100. The vector offset for interrupts
is H'00000600. The vector base address is loaded into the vector base register (VBR) using the
software. The vector base address should reside in the virtual address (P1 or P2).
4.2.3
The exception codes are written to bits 11 to 0 of the EXPEVT register (for reset or general
exceptions) or the INTEVT2 register (for interrupt requests) to identify each specific exception
event. See section 8, Interrupt Controller (INTC), for details of the exception codes for interrupt
requests. Table 4.1 lists exception codes for resets and general exceptions.
4.2.4
The BL bit in SR is set to 1 when a reset or exception is accepted. While the BL bit is set to 1,
acceptance of general exceptions is restricted as described below, making it possible to effectively
prevent multiple exceptions from being accepted.
If the BL bit is set to 1, an interrupt request is not accepted and is retained. The interrupt request
is accepted when the BL bit is cleared to 0. If the CPU is in power-down mode, an interrupt is
accepted even if the BL bit is set to 1 and the CPU returns from power-down mode.
A DMA address error is not accepted and is retained if the BL bit is set to 1 and accepted when the
BL bit is cleared to 0. User break requests generated while the BL bit is set are ignored and are
not retained. Accordingly, user breaks are not accepted even if the BL bit is cleared to 0.
If a general exception other than a DMA address error or user break occurs while the BL bit is set
to 1, the CPU enters a state similar to that in effect immediately after a reset, and passes control to
the reset vector (H'A0000000) (multiple exception). In this case, unlike a normal reset, modules
before the exception handling took place.
Exception Vector Addresses
Exception Codes
Exception Request and BL Bit (Multiple Exception Prevention)
executed, please refer to section 4.5, Usage Notes.
Rev. 1.00, 02/04, page 159 of 804