HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 348

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Note:
10.3.7
DMARS is a 16-bits readable/writable register that specifies the DMA transfer sources from
peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies
for channels 2 and 3.
The DMARS0 and DMARS1 are initialized at reset and retain the current values in standby or
module standby mode.
Transfer requests from the various modules are specified by the MID and RID as shown in table
10.2. When MID/RID other than the values listed in table 10.2 is set, the operation of this LSI is
not guaranteed. The transfer request from the DMARS register is valid only when the resource
select bits (RS3 [3:0]) has been set to B'1000 for CHCR0 to CHCR3 registers. Otherwise, even if
the DMARS has been set, transfer request source is not accepted.
Rev. 1.00, 02/04, page 310 of 804
Bit
16
15 to 0 
*
Bit Name
DME
DMA Extension Resource Selector 0 and 1 (DMARS0 and DMARS1)
Writing 0 is possible to clear the flag.
Initial
Value R/W
0
All 0
R/W
R
Description
DMA Master Enable
DME enables or disables DMA transfers on all channels. If
the DME bit and the DE bit corresponding to each channel in
CHCR are set to 1, transfer is enabled in the corresponding
channel. If this bit is cleared during transfer, transfers in all
the channels can be suspended.
0: Disable DMA transfers on all channels
1: Enable DMA transfers on all channels
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, correct operation
cannot be guaranteed.