HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 290

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 16 bits are always
read in case of a 16-bit device, and 8 bits in case of an 8-bit device. When writing, only the WEn
signal for the byte to be written is asserted.
Reading/writing for cache fill or copy back is performed continuously in total of 16 bytes
according to the specified data bus width. During the processing, bus is not released. If a cache
miss occurs in byte or word operand access or at a branch to an odd word boundary, the CPU
performs longword accesses to perform a cache fill operation on the external interface. Writing to
the write-through area and reading/writing to the area not to be cached are performed according to
the actual access size.
It is necessary to output the data that has been read using the RD signal when a buffer is
established in the data bus. The RD/WR signal is in a read state (high output) when no access has
been carried out. Therefore, care must be taken when controlling the external data buffer, to avoid
collision.
Figures 9.4 and 9.5 show the basic timings of normal space accesses. If the WM bit of the
CSnWCR is cleared to 0, a Tnop cycle is inserted to evaluate the external wait (figure 9.4). If the
WM bit of the CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted
(figure 9.5).
Figure 9.6 and figure 9.7 shows the examples of SRAM connection. Note that bits of external
memory address and those of this LSI address are connected shifted when using the data in
longword units (figure 9.6) and in word units (figure 9.7) since this LSI address is divided in byte
units.
Rev. 1.00, 02/04, page 252 of 804