HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 644

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

20.8
20.8.1
The following points should be noted on EPDR0s in which reception of 8-byte setup data is
performed.
1. Since the setup command must be received in the USB, writing from the USB bus side is prior
2. EPDR0s must be read in 8-byte units. If reading is suspended while it is in progress, data
20.8.2
When the USB cable is disconnected during communication, data which is receiving or
transmitting may remain in the FIFO. Therefore the FIFO must be cleared immediately after
connecting the USB cable again.
Note that the FIFO in which data is receiving from the host or transmitting to the host must not be
cleared.
20.8.3
The following points should be noted when the data register of the USB function controller is read
from or written to.
Receive Data Register: The receive data register must not read data which is more than valid
receive data bytes. That is, data which is more than bytes indicated in the receive data size register
must not be read. In case of the receive data register which has the dual FIFO buffer, the
maximum number of data which can be read in a single time is maximum packet size. Write 1 to
TRG/RDFN after data in the current valid buffer is read. This writing switches the FIFO buffer.
Then, the new number of bytes is reflected in the receive data size and the next data can be read.
Transmit Data Register: The transmit data register must not write data which is more than
maximum packet size. In case of the transmit data register which has the dual FIFO buffer, the
maximum number of data which can be written in a single time is maximum packet size. Write 1
to TRG/PKTE after data is written. This writing switches the FIFO buffer. Then, the next data can
be written to another buffer. Therefore data must not be written in both buffers in a single time.
Rev. 1.00, 02/04, page 606 of 804
to reading from the CPU side. While the CPU reads data after completion of reception and
reception of the next setup command is started, reading from the CPU side is forcibly invalid
in order to give priority to writing. Therefore a value to be read after starting reception is
undefined.
received in the next setup cannot be read successfully.
Usage Notes
Setup Data Reception
FIFO Clear
Overreading/Overwriting of Data Register