HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 310

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Bank Active: The synchronous DRAM bank function is used to support high-speed accesses to
the same row address. When the BACTV bit in SDCR is 1, accesses are performed using
commands without auto-precharge (READ or WRIT). This function is called bank-active function.
When the bank-active function is used, precharging is not performed when the access ends. When
accessing the same row address in the same bank, it is possible to issue the READ or WRIT
command immediately, without issuing an ACTV command. As synchronous DRAM is internally
divided into several banks, it is possible to activate one row address in each bank. If the next
access is to a different row address, a PRE command is first issued to precharge the relevant bank,
then when precharging is completed, the access is performed by issuing an ACTV command
followed by a READ or WRIT command. If this is followed by an access to a different row
address, the access time will be longer because of the precharging performed after the access
request is issued. The number of cycles between issuance of the PRE command and the ACTV
command is determined by the TRP[1:0] bits in CS3WCR.
In a write, when an auto-precharge is performed, a command cannot be issued to the same bank
for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode
is used, READ or WRIT commands can be issued successively if the row address is the same. The
number of cycles can thus be reduced by Trwl + Tap cycles for each write.
There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee
that there will not be a cache hit and another row address will be accessed within the period in
which this value is maintained by program execution, it is necessary to set auto-refresh and set the
refresh cycle to no more than the maximum value of tRAS.
A burst read cycle without auto-precharge is shown in figure 9.17, a burst read cycle for the same
row address in figure 9.18, and a burst read cycle for different row addresses in figure 9.19.
Similarly, a single write cycle without auto-precharge is shown in figure 9.260, a single write
cycle for the same row address in figure 9.21, and a single write cycle for different row addresses
in figure 9.22.
In figure 9.18, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that
issues the READ command. The Tnop cycle is inserted to acquire two cycles of latency for the
DQMn signal that specifies the read byte in the data read from the SDRAM. If the CAS latency is
specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of latency
can be acquired even if the DQMn signal is asserted after the Tc cycle.
When bank active mode is set, if only accesses to the respective banks in area with the bank-active
function set are considered, as long as accesses to the same row address continue, the operation
starts with the cycle in figure 9.17 or 9.20, followed by repetition of the cycle in figure 9.18 or
9.21. An access to a different area during this time has no effect. If there is an access to a different
row address in the bank active state, after this is detected the bus cycle in figure 9.19 or 9.22 is
executed instead of that in figure 9.18 or 9.21. In bank active mode, too, all banks become inactive
after a refresh cycle or after the bus is released as the result of bus arbitration.
Rev. 1.00, 02/04, page 272 of 804