HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 319

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Low-Frequency Mode: When the SLOW bit in SDCR is set to 1, output of commands, addresses,
and write data, and fetch of read data are performed at a timing suitable for operating SDRAM at a
low frequency.
Figure 9.25 shows the access timing in low-frequency mode. In this mode, commands, addresses,
and write data are output in synchronization with the falling edge of CKIO, which is half a cycle
delayed than the normal timing. Read data is fetched at the falling edge of CKIO, which is half a
cycle faster than the normal timing. This timing allows the hold time of commands, addresses,
write data, and read data to be extended.
If SDRAM is operated at a high frequency with the SLOW bit set to 1, the setup time of
commands, addresses, write data, and read data are not guaranteed. Take the operating frequency
and timing design into consideration when making the SLOW bit setting.
D15 to D0
A23 to A0
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
DACK*
RD/WR
DQMn
A11*
CKIO
CKE
RAS
CAS
CS3
BS
2
2. The waveform for DACK is when active low is specified.
1
Tr
Figure 9.25 Low-Frequency Mode Access Timing
Tc1
Td1
Tde
Tap
(High)
Tr
Tc1
Rev. 1.00, 02/04, page 281 of 804
Tnop
Trwl
Tap