HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 589

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

20.3.1
IFR0 is an interrupt flag register for EP0i, EP0o, EP1, EP2i, EP2o, EP3i, EP3o, and EP4 to EP6,
bus reset, setup command reception, VBUS, SUS/RES, SOF, SETC, and SETI. When each flag is
set to 1 and an interrupt is enabled in the corresponding bit of the interrupt enable register 0
(IER0), an interrupt occurs from the INT pin specified by the corresponding bit in the interrupt
select register (ISR0). Interrupt requests and interrupt request signals can be specified by ISR0.
Clearing is performed by writing 0 to the bit to be cleared. Writing 1 is not valid and nothing is
changed.
Bit
31
30
29
28
Bit Name

BRST
SETUP TS 0
VBUS MN
Interrupt Flag Register 0 (IFR0)
Initial
Value
0
0
0
R/W
R
R/W
R/W
R*
2
Description
Reserved
This bit is always read as 0. The write value should
always be 0. If 1 is written to this bit, correct operation
cannot be guaranteed.
Bus reset
[Setting condition]
•
[Clearing conditions]
•
•
Setup command receive complete
[Setting condition]
•
[Clearing conditions]
•
•
USB Connection Status
Status bit to monitor the USB_VBUS pin state. Reflects
the state of the USB_VBUS pin.
When a bus reset signal is detected on the USB bus.
At a reset
When 0 is written to by CPU
When 8-byte data that decodes the command by the
function is normally received and an ACK handshake
is returned to the host from the function.
At a reset
When 0 is written to by CPU
Rev. 1.00, 02/04, page 551 of 804