HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 24

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 4 Exception Handling
Figure 4.1 Register Bit Configuration ........................................................................................ 156
Section 5 Cache
Figure 5.1 Cache Structure ......................................................................................................... 177
Figure 5.2 Cache Search Scheme ............................................................................................... 183
Figure 5.3 Write-Back Buffer Configuration.............................................................................. 185
Figure 5.4 Specifying Address and Data for Memory-Mapped Cache Access .......................... 188
Section 8 Interrupt Controller (INTC)
Figure 8.1 Block Diagram of INTC............................................................................................ 200
Figure 8.2 Interrupt Operation Flowchart................................................................................... 215
Section 9 Bus State Controller (BSC)
Figure 9.1 BSC Functional Block Diagram................................................................................ 219
Figure 9.2 Logical Address Space and Physical Address Space ................................................ 221
Figure 9.3 Normal Space Basic Access Timing (Access Wait 0)............................................... 251
Figure 9.4 Continuous Access for Normal Space 1 Data Bus Width = 16 bits,
Figure 9.5 Continuous Access for Normal Space 2 Data Bus Width = 16 bits,
Figure 9.6 Example of 16-Bit Data-Width SRAM Connection.................................................. 255
Figure 9.7 Example of 8-Bit Data-Width SRAM Connection.................................................... 255
Figure 9.8 Wait Timing for Normal Space Access (Software Wait Only) ................................. 256
Figure 9.9 Wait State Timing for Normal Space Access
Figure 9.10 CSn Assert Period Expansion.................................................................................. 258
Figure 9.11 Example of 16-Bit Data-Width SDRAM Connection ............................................. 260
Figure 9.12 Burst Read Basic Timing (Auto Pre-charge)........................................................... 268
Figure 9.13 Burst Read Wait Specification Timing (Auto Pre-charge)...................................... 268
Figure 9.14 Single Read Wait Specification Timing (Auto Pre-charge) .................................... 269
Figure 9.15 Basic Timing for Synchronous DRAM Burst Write (Auto Pre-charge).................. 270
Figure 9.16 Single Write Basic Timing (Auto-Precharge) ......................................................... 271
Figure 9.17 Burst Read Timing (No Auto Precharge) ................................................................ 273
Figure 9.18 Burst Read Timing (Bank Active, Same Row Address) ......................................... 273
Figure 9.19 Burst Read Timing (Bank Active, Different Row Addresses) ................................ 274
Figure 9.20 Single Write Timing (No Auto Precharge).............................................................. 275
Figure 9.21 Single Write Timing (Bank Active, Same Row Address)....................................... 276
Figure 9.22 Single Write Timing (Bank Active, Different Row Addresses).............................. 277
Figure 9.23 Auto-Refresh Timing .............................................................................................. 278
Figure 9.24 Self-Refresh Timing ................................................................................................ 280
Figure 9.25 Low-Frequency Mode Access Timing .................................................................... 281
Figure 9.26 Power-Down Mode Access Timing ........................................................................ 282
Figure 9.27 Synchronous DRAM Mode Write Timing (Based on JEDEC)............................... 284
Rev. 1.00, 02/04, page xxiv of xxxviii
Long-Word Access, CSnWCR.WN Bit = 0 (Access Wait = 0, Cycle Wait = 0) ...... 253
Long-Word Access, CSnWCR.WN Bit = 1 (Access Wait = 0, Cycle Wait = 0) ...... 254
(Wait State Insertion using WAIT Signal) ................................................................ 257