HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 478

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

16.3.1
SCRSR is the register used to receive serial data.
The SCIF sets serial data input from the RxD pin in SCRSR in the order received, starting with the
LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to the receive FIFO data register, SCFRDR, automatically.
SCRSR cannot be directly read or written to by the CPU.
16.3.2
SCFRDR is a 64-stage 8-bit FIFO register that stores received serial data (receive FIFO).
When the SCIF has received one byte of serial data, it transfers the received data from SCRSR to
SCFRDR where it is stored, and completes the receive operation. SCRSR is then enabled for
reception, and consecutive receive operations can be performed until the receive FIFO data
register is full (64 data bytes).
SCFRDR is a read-only register, and cannot be written to by the CPU.
If a read is performed when there is no receive data in the receive FIFO data register, an undefined
value will be returned. When the receive FIFO data register is full of receive data, subsequent
serial data is lost.
16.3.3
SCTSR is the register used to transmit serial data.
To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR to
SCTSR, then sends the data sequentially to the TxD pin starting with the LSB (bit 0).
When transmission of one byte is completed, the next transmit data is transferred from SCFTDR
to SCTSR, and transmission is started automatically.
SCTSR cannot be directly read or written to by the CPU.
Rev. 1.00, 02/04, page 440 of 804
Bit
7 to 0
Bit Name
SCFRD7 to SCFRD0 Undefined R
Receive Shift Register (SCRSR)
Receive FIFO Data Register (SCFRDR)
Transmit Shift Register (SCTSR)
Initial
Value
R/W
Description
Serial Receive Data FIFO