HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 469

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 15.13 States of Transmit and Receive Operations in SPI Mode
Note: In SPI mode, settings other than the above are prohibited.
In half-duplex reception (transmission is disabled), the value output from the MOSI can be
controlled by the TXDIZ bit in SIMDR as follows.
TXDIZ = 0: Transmission is disabled, 1 is output on the MOSI.
TXDIZ = 1: Transmission is disabled, the MOSI is in the high-impedance state.
TXE
0
0
1
1
RXE
0
1
0
1
TDMAE
Don't care
0
0
1
0
RDMAE
Don't care
1
0
0
0
SPI Transmit/Receive Operation
Transmission/reception is disabled
Half-Duplex Reception
The transmit FIFO does not operate and dummy data is
transmitted from the MOSI. Data received at the MISO is
stored in the receive FIFO and is transferred by using the
DMA.
Receive operation continues as long as RE bit = 1; the
receive-FIFO overflow (RFOVF) status is set after the
receive FIFO has become full and further receive data is
ignored.
Half-Duplex Transmission
The data in the transmit FIFO is transmitted from the
MOSI. The receive FIFO does not operate, and data on
the MISO is ignored. When the transmit FIFO becomes
empty, the transmit operation is completed.
Half-Duplex Transmission
The data which has been transferred by using the DMA
to the transmit FIFO is transmitted from the MOSI. The
receive FIFO does not operate and data on the MISO is
ignored. When the transmit FIFO becomes empty, the
transmit operation is completed.
Full-Duplex Communication
The transmit and receive FIFOs operate at the same
time. Data in the transmit FIFO are transmitted or
received. When there is no data left in the transmit FIFO,
the transmit and receive operations are completed.
Rev. 1.00, 02/04, page 431 of 804