HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 194

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HD6417660

Manufacturer Part Number
HD6417660
Description
Renesas 32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Figure 4.1 shows the bit configuration of each register.
4.1.1
TRA is assigned to address H'FFFFFFD0 and consists of the 8-bit immediate data (imm) of the
TRAPA instruction. TRA is automatically specified by the hardware when the TRAPA
instruction is executed. Only bits 9 to 2 of the TRA can be re-written using the software.
Rev. 1.00, 02/04, page 156 of 804
Bit
31 to 10 
9 to 2
1
0
TRAPA Exception Register (TRA)
Bit Name
TRA
31
31
31
31
Initial Value
All 0
All 0
Figure 4.1 Register Bit Configuration
0
0
0
R/W
R
R/W
R
TEA
12 11
12 11
10 9
Description
Reserved
These bits are always read as 0. The write value
should always be 0. If 1 is written to these bits,
correct operation cannot be guaranteed.
8-bit Immediate Data
Reserved
These bits are always read as 0. The write value
should always be 0. If 1 is written to these bits,
correct operation cannot be guaranteed.
EXPEVT
INTEVT2
TRA
2 1 0
0
0
0
0
TRA
EXPEVT
INTEVT2
TEA

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