HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 263

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

9.4.1
CMNCR is a 32-bit register that controls the common items for each area. CMNCR is initialized
by a power-on reset, but not by a manual reset or in standby mode and holds the previous value.
Do not access external memory other than area 0 until the CMNCR register initialization is
complete.
Bit
31 to 8 
7
6
5
4
Bit Name
DMAIW1
DMAIW0
DMAIWA

Common Control Register (CMNCR)
0
Initial
Value
All 0
0
0
1
R/W Method of inserting wait states between access cycles when
R/W Description
R
R/W
R/W
R
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, correct operation
cannot be guaranteed.
Wait states between access cycles when DMA single
address transfer is performed
Specify the number of idle cycles to be inserted after an
access to an external device with DACK when DMA single
address transfer is performed. The method of inserting idle
cycles depends on the contents of DMAIWA.
00: No idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 4 idle cycled inserted
DMA single address transfer is performed
Specifies the method of inserting the idle cycles specified by
the DMAIW1 and DMAIW0 bits. Clearing this bit will make
this LSI insert the idle cycles when another device, which
includes this LSI, drives the data bus after an external device
with DACK drove it. Setting this bit will make this LSI insert
the idle cycles even when the continuous accesses to an
external device with DACK are performed.
0: Idle cycle is inserted when other device drives the data
1: Idle cycle is inserted every time when an external device
Reserved
This bit is always read as 1. The write value should always
be 1. When 0 is written to this bit, correct operation cannot
be guaranteed.
bus after an external device with DACK drives the data
bus.
with DACK is accessed.
Rev. 1.00, 02/04, page 225 of 804