HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 210

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Illegal Instruction Exception in Repeat Control Period: If one of the following instructions is
executed at the address following RptDtct1, a general illegal instruction exception occurs. For
details on an address to be saved in the SPC, refer to section 4.4.3, Exception in Repeat Control
Period.
• Branch instructions
• Repeat control instructions
• Load instructions for SR, RS, and RE
Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat
An Exception Retained in Repeat Control Period: In the repeat control period, an interrupt or
some exception will be retained to prevent an exception acceptance at an instruction where
returning from the exception cannot be performed correctly. For details, refer to repeat loop
program examples (1) to (4). In the examples, exceptions generated at instructions indicated as
[B], and [C] ([C1] or [C2]) the following processing is executed.
• Interrupt, DMA address error
Note: An interrupt request or a DMA address error exception request is retained in the interrupt
• User break before instruction execution
Rev. 1.00, 02/04, page 172 of 804
BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA
SETRC, LDRS, LDRE
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+, Rs
An exception request is not accepted and retained at instructions [B] and [C]. If an instruction
indicates as [A] is executed the next time, an exception request is accepted.
examples (1) to (4), any interrupt or DMA address error cannot be accepted in a repeat loop
consisting of four instructions or less.
A user break before instruction execution is accepted at instruction [B], and an address of
instruction [B] is saved in the SPC. This exception cannot be accepted at instruction [C] but
the exception request is retained until an instruction [A] or [B] is executed the next time.
Then, the exception request is accepted before an instruction [A] or [B] is executed. In this
case, an address of instruction [A] or [B] is saved in the SPC.
detection instructions and all the remaining instructions. In a repeat loop consisting of
four or more instructions, restrictions apply to only the three instructions that include a
repeat end instruction.
controller (INTC) and the direct memory access controller (DMAC) until the CPU can
accept a request.
*
As shown in