HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 323

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

9.5.6
The burst ROM interface is used to access a memory with a high-speed read function using a
method of address switching called the burst mode or page mode. In a burst ROM interface,
basically the same access as the normal space interface is performed, but the 2nd and subsequent
accesses are performed only by changing the address, without negating the RD signal at the end of
the 1st cycle. In the 2nd and subsequent accesses, addresses are changed at the falling edge of the
CKIO signal.
For the 1st access cycle, the number of wait cycles specified by the W[3:0] bits of the CSnWCR
register is inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified
by the BW[1:0] bits of the CSnWCR register is inserted.
In the access to the burst ROM, the BS signal is asserted only to the first access cycle. An external
wait input is valid only to the first access cycle. In the single access or write access that do not
perform the burst operation in the page flash ROM interface, access timing is same as a normal
space interface. Table 9.12 lists a relationship between bus width, access size, and the number of
bursts. Figure 9.28 shows a timing chart.
Table 9.12 Relationship between Data Bus Width, Access Size, and Number of Bursts
Data Bus Width
8 bits
16 bits
Burst ROM Interface
Access Size
8 bits
16 bits
32 bits
16 bytes
8 bits
16 bits
32 bits
16 bytes
Number of Bursts
1
2
4
16
1
1
2
8
Rev. 1.00, 02/04, page 285 of 804
Number of Accesses
1
1
1
1
1
1
1
1