HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 455

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

15.4.6
Overview: The transmit and receive FIFOs of the SIOF have the following features.
• 16-stage 32-bit FIFOs for transmission and reception
• The FIFO pointer can be updated in one read or write cycle regardless of access size of the
Transfer Request: The transfer request of the FIFO can be issued to the CPU or DMAC as the
following interrupt sources.
• FIFO transmit request: TDREQ (transmit interrupt source)
• FIFO receive request: RDREQ (receive interrupt source)
The request conditions for FIFO transmit or receive can be specified individually. The request
conditions for the FIFO transmit and receive are specified by the TFWM2 to TFWM0 bits and
RFWM2 to RFWM0 bits in SIFCTR, respectively. Tables 15.9 and 15.10 summarize the
conditions specified by SIFCTR.
Table 15.9 Conditions to Issue Transmit Request
TFWM2 to TFWM0
000
100
101
110
111
SIOFSYNC
SIOFTXD
SIOFRXD
SIOFSCK
CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.)
FIFO
Specifications: TRMD[1:0]=01,
Normal FS
L-channel
No.0
data
Slot
Figure 15.8 Control Data Interface (Secondary FS)
TDLE=1,
RDLE=1,
CD0E=1,
Number of
Requested Stages
1
4
8
12
16
LSB=1 (Secondary FS request)
1/2 frame
REDG=0,
TDLA[3:0]=0000,
RDLA[3:0]=0000,
CD0A[3:0]=0000,
1 frame
Transmit Request
Empty area is 16 stages
Empty area is 12 stages or more
Empty area is 8 stages or more
Empty area is 4 stages or more
Empty area is 1 stage or more
Secondary FS
channel 0
Control
FL[3:0]=1110 (Frame length: 128 bits),
TDRE=0,
RDRE=0,
CD1E=0,
No.0
Slot
Rev. 1.00, 02/04, page 417 of 804
TDRA[3:0]=0000,
RDRA[3:0]=0000,
CD1A[3:0]=0000
1/2 frame
Used Areas
Smallest
Largest
Normal FS