HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 286

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

9.5
9.5.1
This LSI supports big endian, in which the 0 address is the most significant byte (MSByte) in the
byte data and little endian, in which the 0 address is the least significant byte (LSByte) in the byte
data. Endian is specified on power-on reset by the external pin (MD5). When MD5 pin is low
level on power-on reset, the endian will become big endian and when MD5 pin is high level on
power-on reset, the endian will become little endian.
Two data bus widths (8 bits and 16 bits) are available for normal memory and byte-selection
SRAM. Note that the data bus width for the area 0 is fixed 16 bits. The data bus width of SDRAM
is fixed 16 bits. Data alignment is performed in accordance with the data bus width of the device
and endian. This also means that when longword data is read from a byte-width device, the read
operation must be done four times. In this LSI, data alignment and conversion of data length is
performed automatically between the respective interfaces.
Table 9.3 through 9.6 show the relationship between endian, device data width, and access unit.
Table 9.3
Rev. 1.00, 02/04, page 248 of 804
Operation
Byte access at 0
Byte access at 1
Byte access at 2
Byte access at 3
Word access at 0
Word access at 2
Longword
access at 0
Endian/Access Size and Data Alignment
Operating Description
16-Bit External Device/Big Endian Access and Data Alignment
1st time at 0
2nd time at 2
D15 to D8
Data 7 to 0

Data 7 to 0

Data 15 to 8
Data 15 to 8
Data 31 to 24
Data 15 to 8
Data Bus
D7 to D0

Data 7 to 0

Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 23 to 16
Data 7 to 0
WE1/DQM1
Assert

Assert

Assert
Assert
Assert
Assert
Strobe Signals
WE0/DQM0

Assert

Assert
Assert
Assert
Assert
Assert