HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 354

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Choose to detect DREQ by either the edge or level of the signal input with the DREQ level (DL)
bit and DS bit of CHCR_0 as shown in table 10.4. The source of the transfer request does not have
to be the data transfer source or destination.
Table 10.4 Selecting External Request Detection with DL, DS Bits
When DREQ is accepted, the DREQ pin becomes request accept disabled state (non-sensitive
period). After issuing acknowledge signal DACK for the accepted DREQ, the DREQ pin again
becomes request accept enabled state.
When DREQ is used by level detection, there are following two cases by the timing to detect the
next DREQ after outputting DACK.
Overrun0: Transfer is aborted after the same number of transfer has been performed as requests.
Overrun1: Transfer is aborted after transfers have been performed for (the number of requests plus
1) times.
The DO bit in CHCR selects this overrun 0 or overrun 1. (Table 10.5)
Table 10.5 Selecting External Request Detection with DO Bit
On-Chip Peripheral Module Request: In this mode (table 10.6), the transfer is performed in
response to the transfer request signal (interrupt request signal) of an on-chip peripheral module.
Transfer request signals comprise the transmit data empty transfer request and receive data full
transfer request from the SCIF0, SCIF1, SIOF, and USBF.
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0,
NMIF = 0), a transfer is performed upon the input of a transfer request signal.
Rev. 1.00, 02/04, page 316 of 804
DL
0
1
CHCR
DO
0
1
CHCR
DS
0
1
0
1
Detection of External Request
Low level detection
Falling edge detection
High level detection
Rising edge detection
External Request
Overrun 0
Overrun 1