HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 297

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

9.5.5
SDRAM Interface
SDRAM Direct Connection: The SDRAM that can be connected to this LSI is a product that has
11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin
for setting precharge mode in read and write command cycles. The control signals for direct
connection of SDRAM are RAS, CAS, RD/WR, DQM1, DQM0, CKEand CS3. All the signals
other than CS3 are common to all areas, and signals other than CKE are valid when CS3 is
asserted. The data bus width of the area that is connected to SDRAM should be set to16 bits.
Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as
the SDRAM operating mode.
Commands for SDRAM can be specified by RAS, CAS, RD/WR, and specific address signals.
These commands are shown below.
• NOP
• Auto-refresh (REF)
• Self-refresh (SELF)
• All banks pre-charge (PALL)
• Specified bank pre-charge (PRE)
• Bank active (ACTV)
• Read (READ)
• Read with pre-charge (READA)
• Write (WRIT)
• Write with pre-charge (WRITA)
• Write mode register (MRS)
The byte to be accessed is specified by DQM1 and DQM0. Reading or writing is performed for a
byte whose corresponding DQMn is low. For details on the relationship between DQMn and the
byte to be accessed, refer to section 9.5.1, Endian/Access Size and Data Alignment.
Figures 9.11 shows as example of the connection of the SDRAM with this LSI. Address area of
this LSI is allocated in byte units. Therefore, note that bit addresses of an external memory and
those of this LSI differ when handling data in longword units or word units.
Rev. 1.00, 02/04, page 259 of 804