HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 405

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 13.3 Register States in Software Standby Mode
2. Canceling Software Standby Mode
Note: * This standby mode can be canceled by the reset from the RESETP pin.
Module
Interrupt controller (INTC)
Bus state controller (BSC)
DMAC
Clock pulse generator (CPG)
Timer Unit (TMU)
SIOF, SCIF0, SCIF1
USBPM, USBH, USBF
D/A converter (DAC)
I/O port
User break controller (UBC)
H-UDI
The procedure for switching to software standby mode is as follows:
1. Clear the TME bit in the WDT’s timer control register (WTCSR) to 0 to stop the WDT.
2. Set the WDT’s timer counter (WTCNT) to 0 and the CKS2 to CKS0 bits in the WTCSR
3. After the STBY bit in the STBCR register is set to 1, a SLEEP instruction is executed.
Software standby mode is canceled by interrupts (NMI, IRQ) or a reset.
 Canceling with an Interrupt
register to appropriate values to secure the specified oscillation settling time.
The on-chip WDT can be used for hot starts. When the chip detects an NMI or IRQ
interrupt, the clock will be supplied to the entire chip and software standby mode canceled
after the time set in the WDT’s timer control/status register has elapsed. Interrupt handling
then begins and a code indicating the interrupt source is set in the INTEVT2 registers.
After the branch to the interrupt handling routine, clear the STBY bit in the STBCR
register. WTD stops automatically. If the STBY bit is not cleared, WTD continues
operation and a transition is made to software standby mode* when the WTCNT reaches
H'80. Interrupts are accepted in software standby mode even when the BL bit in the SR
register is 1. If necessary, save SPC and SSR to the stack before executing the SLEEP
instruction.
Immediately after an interrupt is detected, the phase of the CKIO pin clock output may be
unstable, until the software standby mode is canceled when the CKOEN bit in the FRQCR
register and the HIZCNT bit in the CMNCR register are set to 1.
Registers Initialized




TSTR register






Rev. 1.00, 02/04, page 367 of 804
Registers Retaining Data
All registers
All registers
All registers
All registers
Except TSTR register
All registers
All registers
All registers
All registers
All registers
All registers