HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 645

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

20.8.4
The EP0 interrupt sources assigned to IFR0 (bits 0, 1, 2, and 29) must be assigned to the same
interrupt pins by ISR0. The other interrupt sources have no restrictions.
20.8.5
When the DMA transfer is enabled in endpoints 2o and 6, the data register cannot be cleared.
Cancel the DMA transfer before clearing the data register.
20.8.6
The bulk-in transfer has a transfer request interrupt (TR interrupt). The following points should be
noted when using a TR interrupt.
When the IN token is sent from the USB host and there is no data in the corresponding EP FIFO,
the TR interrupt flag is set. However, the TR interrupt is generated continuously at the timing as
shown in figure 20.20. In this case, note that erroneous operation should not occur.
Note: When the IN token is received and there is no data in the corresponding EP FIFO, an
NACK is determined. However, the TR interrupt flag is set after an NACK handshake is
transmitted. Therefore when the next IN token is received before TRG/PKTE is written,
the TR interrupt flag is set again.
Note on Using TR Interrupt
Assigning EP0 Interrupt Sources
FIFO Clear when DMA Transfer is Set
Rev. 1.00, 02/04, page 607 of 804