HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 316

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

2. Self-refreshing
Rev. 1.00, 02/04, page 278 of 804
After starting, the auto refreshing, PALL command is issued in the Tp cycle to make all the
banks to pre-charged state from active state after waiting for the completion when some bank
is being pre-charged. Then REF command is issued in the Trr cycle after inserting idle cycles
of which number is specified by the TRP[1:0] bits in CS3WCR. A new command is not issued
for the duration of the number of cycles specified by the TRC[1:0] bits in CS3WCR after the
Trr cycle. The TRC[1:0] bits must be set so as to satisfy the SDRAM refreshing cycle time
stipulation (tRC). A NOP cycle is inserted between the Tp cycle and Trr cycle when the
setting value of the TRP[1:0] bits in CS3WCR is longer than or equal to 2 cycles.
Self-refresh mode in which the refresh timing and refresh addresses are generated within the
SDRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in
SDCR to 1. After starting the self-refreshing, PALL command is issued in Tp cycle after the
completion of the pre-charging bank. A SELF command is then issued after inserting idle
cycles of which number is specified by the TRP[1:0] bits in CS3WSR. The SDRAM cannot be
accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE
bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the
number of cycles specified by the TRC[1:0] bits in CS3WCR.
D15 to D0
A23 to A0
DACK*
RD/WR
DQMn
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
A11*
CKIO
RAS
CAS
CS3
BS
1
2
2. The waveform for DACK is when active low is specified.
Figure 9.23 Auto-Refresh Timing
PALL
Tp
Tpw
REF
Trr
Hi-z
Trc
Trc
Trc